1. Field of the Invention
The present invention relates to a substrate processing apparatus and a substrate processing method for carrying out a photolithography process for a semiconductor wafer or a glass substrate (LCD substrate) for a liquid crystal display.
2. Description of the Related Art
A substrate processing apparatus (system) is configured in combination between a coating and developing device and an exposure device in order to execute a series of processes applying a photolithography technique. For example, a conventional system described in U.S. Pat. No. 6,507,770 comprises a carrier placement block 1A, a process block 1B, an interface block 1C, and an exposure system 1D, as shown in FIG. 1. A wafer W is taken out from a carrier C of the carrier placement block 1A by a delivery arm 11. The taken-out wafer is transported to the process block 1B via a delivery unit of a rack unit 13a. Subsequently, the transported wafer is transported and processed in a predetermined processing unit in a predetermined order, and the wafer is coated with a resist liquid. Thereafter, the coated wafer is transported to the exposure system 1D via the interface block 1C, and a resist film is subjected to pattern exposure. Then, the wafer W is returned to the process block 1B again after the exposure, is subjected to post exposure baking process (PEB) by a baking unit. The baked wafer is cooled by a cooling unit, and is processed to be developed by a developing unit.
In the meantime, in a conventional system, a plurality wafers W are continuously processed in parallel. Thus, in the system, a transfer schedule of the wafers W is programmed in advance so that the wafers W are transported through a predetermined passage. The transfer schedule is predetermined so that, when a plurality of wafers W (all the wafers in one lot or all the wafers belonging to a plurality of lots) are continuously processed in parallel, each of the wafers W is transported to a predetermined module at a predetermined timing. All the wafers in the system are transferred in accordance with this transfer schedule.
A conventional transfer schedule will be described with reference to FIG. 2A. The conventional transfer schedule is provided as a table showing in time series timings of transferring wafers W1 to W7 to a previous module MOD and three multi-modules (MOD1, MOD2, MOD3). The wafer 1 indicates a first wafer in the lot, and the wafer 2 indicates a second wafer in the lot, respectively.
Now, how to read the transfer schedule will be briefly described here. In a phase 1 of FIG. 2A, there is shown that the wafer W1 is transported to the previous module MOD. In a phase 2, there is shown that the wafer W1 is transported to the multi-module MOD1, and the wafer W2 is transported to the previous module MOD, respectively.
Here, transfer means comprises two or more arms. Thus, the wafer is received by one arm with respect to one module, and then, the wafer is delivered by the other arm. Therefore, in a phase 5, the transfer means receives the wafer W4 in the previous module MOD by one arm, transports the wafer W5 to the previous module MOD by the other arm, and transports the wafer W4 held by the one arm to the multi-module MOD1. In the multi-module MOD1, the transfer means first receives the wafer W1 in the multi-module MOD1 by the other arm thereof, and delivers the wafer W4 held by the one arm to the module MOD1. In this manner, a replacing operation between the wafer W1 and the wafer W4 is carried out in the multi-module MOD1, and the wafer W1 exported from the multi-module MOD1 is transported to a module in a next process of the multi-module by the transfer means.
Here, in order to enhance throughput, in the transfer schedule, when subsequent wafers are transported to multi-modules in which preceding wafers in the same lot have been processed, scheduling is carried out so as to always carry out a replacing operation.
In the meantime, in the exposure system 1D, when a time is required for reticule replacement while in lot change or when an alarm sounds, a wafer may not be exported from the exposure device at a predetermined timing in accordance with the transfer schedule. A delay time of processing in the exposure system 1D cannot be recognized in a module at the side of a processing block 1B. Thus, there is a case in which the wafer W cannot be transferred in accordance with the original transfer schedule. At this time, the transfer schedule is currently changed as shown in FIG. 2B.
This transfer schedule shows an example in which delivery of the wafer W2 in the phase 2 is delayed, and the wafer W2 is transported to the previous module MOD in the phase 3. If delivery of the wafer W2 is thus delayed, the wafer 2 is transported to the multi-module MOD2 in the phase 4. Thus, a timing at which the subsequent wafer W3 is transported to the multi-modules MOD1 to MOD3 is shifted to an immediately following phase in order. In this manner, in the phase 5, a blank occurs at the multi-module MOD1, so that, when the wafer W4 is transported to the multi-module MOD1, the replacing operation between the wafer W1 and the wafer W4 cannot be carried out.
Namely, in the phase 5, the transfer means receives the wafer W3 in the previous module MOD by one arm, and delivers the wafer W4 to the previous module MOD by the other arm. Then, the transfer means transfers the wafer W3 held by the one arm, receives the processed wafer W1 from the multi-module MOD1, and transfers the wafer 1 to a module in a next process. Then, in the phase 6, the transfer means receives the wafer W4 in the previous module MOD, delivers the wafer W5 to the previous module MOD, and transfers the wafer W4 to the multi-module MOD1. At this time, in the multi-module MOD1, although the wafer W1 does not exist because the wafer has been exported in the phase 5, the transfer means always operates so as to first receive a wafer from a module, and then, deliver the wafer to the module. Therefore, freewheeling wafer taking operation (an operation in which a wafer is not actually held) is carried out by one arm of the transfer means, and the wafer W4 of the one arm is delivered to the multi-module MOD1.
In this manner, in the multi-module MOD1, the wafer W1 and the wafer W4 cannot be replaced with each other, and a process for receiving the wafer W1 from the multi-module MOD1 and a freewheeling taking process in the multi-module MOD1 will increase. Thus, as described previously, if there occurs a case in which delivery for the previous module MOD is delayed, the replacing operation cannot be carried out. Therefore, there occurs a danger that throughput is lowered.